Intel Corp. and Micron Technology Inc. plan to announce the world’s first 25-nanometer NAND flash technology, which will make it possible to double the storage capacity of devices like smartphones, music and media players, and solid-state drives (SSD) without making the products themselves any bigger.
Intel is currently shipping samples to equipment manufacturers of an 8GB NAND die created with its latest lithography. Lithography is the process of creating cells and transistors in silicon, which are used to store bits of data. The smaller they are, the more that can fit on a single NAND flash chip — and the greater the storage capacity.
The companies plan to begin mass production of the 8GB die next quarter.
"This will help speed the adoption of solid-state drive solutions for computing," Tom Rampone, vice president and general manager of Intel’s NAND solutions group, said in a statement.
The new 25nm 8GB die, which measures 0.35-in. by 0.74-in., is made up of many, smaller 64Gbit NAND chips. The new NAND technology makes it possible to build products using half as many chips as is possible with the current 34nm lithography technology, allowing for smaller, higher-density designs. For example, a 256GB SSD can be built with 32 of the 8GB NAND flash dies instead of 64 dies; a 32GB smartphone needs just four dies; and a 16GB flash card requires only two. The change also cuts the overall cost to produce mobile products.
The die is "small enough to fit through the hole in the middle of a compact disc, yet packs more than 10 times the data capacity of that CD," Troy Winslow, director of NAND marketing at Intel, said. A standard CD holds 700MB of data.
Intel said its 25nm lithography process is not only the smallest for NAND flash memory technology but it’s also the overall smallest semiconductor technology in existence. That means its manufacturing process will lend itself to advances in the more general area of consumer electronics and computing applications.
A NAND flash wafer made with 25nm lithography.
The new NAND flash product was manufactured by Intel and Micron’s joint venture IM Flash Technologies (IMFT).
In October, the company announced what it called its highest performing SSD product based on that technology. The SSD chips represented a sixfold improvement in endurance over the previous generation of technology. In that announcement, a spokeswoman also alluded to the possibility that the SSD chips could be placed directly on a computer’s motherboard, making it possible to bypass the slower SATA drive interface.
The 25nm flash product uses Version 2.2 of the Open NAND Flash Interface (ONFI) specification, which currently has a data transfer rate of 200MB/sec. Kilbuck said IMFT is working on qualifying a future NAND flash product for ONFI’s 3.0 specification, which has a data throughput rate of 400MB/sec.
The newest memory has the same endurance as the previous 34nm technology, with 5,000 write-erase cycles, Winslow said.
Future hurdles
Both Micron and Intel admitted during a news conference on Friday that they’re coming up against considerable technology hurdles in their attempts to continue to reduce the size of NAND flash memory. At 25nm, IMFT is approaching atomic sizes. For example, a human hair is 3,000 times thicker than 25nm. If the thickness of a human hair was one mile, 25nm would be about 20 inches, according to Kevin Kilbuck, director of NAND marketing at Micron.
"At 34nm, we were six to 12 months ahead of the competition, and with 25nm we believe we’ll extend that lead," Kilbuck said.
IMFT has doubled NAND density roughly every 18 months. The company began production in 2006 using a 50nm lithography process, and in 2008 it announced a 34nm flash chip based on multilevel cell (MLC) NAND that could store 32Gbit. That chip stored two bits of data per cell.
Last August, IMFT announced a new three-bit-per-cell, NAND flash memory technology using its 34nm lithography process. The advancement represented an 11% reduction in NAND flash size. However, because of reliability issues, IMFT chose to discontinue production of a three-bit MLC NAND flash product, Kilbuck said.
The 25nm NAND chips hold two bits per memory cell.
"The challenge of stepping down in lithography is to continue to provide equivalent performance… as previous products," Winslow said. "Those were challenges we were able to overcome with this generation. But looking into the next couple of generations, we do recognize materials and process technology will have to change as obstacles mount."
IMFT is currently considering other memory technologies for future products, such as charge trap flash and 3D-cell NAND.
"It’s just something we’re looking at to extend the life of the NAND cell itself," Kilbuck said. "If we do end up going that route, we can leverage our DRAM process technology and cell technology, since DRAM has been utilizing a 3D-cell with some fine geometries. The goal is to keep scaling so we can stay ahead in cost."
The new lithography process allows for half the number of flash chips to build current solid state products
